Design of Four Bit Shift Register by using D Flip Flop in 16nm Predictive Technology Model

Effective sequential circuit designs are becoming more and more necessary as the requirement for high-speed, low-power digital sys- tems grows. This paper describes the use of D flip-flops in Cadence Vir- tuoso with 16nm Predictive Technology Model (PTM) parameters to create a 4-bit Parallel-In Parallel-Out (PIPO) shift register. The design is tested for power, delay, and frequency performance and shows depend- able data storage and sequential shifting. The results of the simulation demonstrate definite advantages over the CMOS nodes, including a 80% decrease in power consumption, a 80% improvement in propagation de- lay, and a significant rise in maximum operating frequency up to 40-60 GHz with additional area savings.The implementation and analysis of a 4-bit shift register employing 16nm PTM-based FinFET technology, demonstrating its appropriateness for high-speed and low-power VLSI applications, constitutes the uniqueness of this study.