A High-Resolution 64-Multi-Phased Time-to-Digital Converter Architecture Implemented on a Cyclone V FPGA

This paper presents the design and implementation of a 64-Multi-Phased Time-to-Digital Converter (TDC64) architecture on a low-cost Cyclone V FPGA. Operating at 500 MHz, the architecture successfully achieves a theoretical resolution of 31.25 picoseconds (ps). The modular design leverages a multi-phased counter methodology to significantly enhance temporal granularity. The performance was comprehensively characterized in two stages. Internal analysis, using the Signal Tap Logic Analyzer, confirmed the design's integrity, yielding a measurement result of 9660 for a 300 ns interval, representing a low deviation of approximate 0.62 %. Linearity tests conducted over a 20 ns span showed excellent performance with differential nonlinearity (DNL) ranging from +0.053 to -0.101 and integral nonlinearity (INL) between -0.192 and -0.218. External testing, utilizing a waveform generator and oscilloscope, revealed an uncompensated resolution of 47.43 ps (34 % deviation). Mitigating the noise, the compensated resolution for an interval of 300 ns result in 9,596, a resolution of 31.263 picoseconds, which represents 0.04%. A remarkable result close to the theoretically expected value. The mean values were employed to evaluate the linearity, yielding DNL of +0,0560 and -0,0129, as well as INL of +0,0484 and -0,2104. Representing high linearity and high resolution compared with a previous noisy entry signal. This work demonstrates that high-end timing performance is attainable on cost-effective FPGA platforms.