High-Performance Lock-In Detection on FPGA Using Coherent Averaging

Coherent detection techniques are widely used to extract weak periodic signals embedded in noise, with lock-in amplification being one of the most established approaches. In this work, coherent averaging stage followed by lock-in detection is analyzed as an alternative architecture. Building on previous results that demonstrate the mathematical equivalence between classical lock-in detection using moving-average filters and this approach, this paper focuses on the implications of this equivalence from an implementation perspective.A detailed analysis of arithmetic operation counts shows that concentrating the averaging process in the coherent stage significantly reduces the number of required multiplications. The impact of this trade-off is evaluated through FPGA implementations, comparing timing performance and resource utilization between both architectures under different parameter configurations. The results show that the proposed implementation improves the maximum operating frequency by approximately 40%, at the expense of higher memory requirements.The approach is further validated through open-source implementations on different SoC-FPGA platforms, whose measurement results closely match both theoretical predictions and those obtained using a commercial lock-in amplifier. These results demonstrate that architectures based on coherent averaging followed by lock-in detection enable high-performance, cost-effective and reproducible coherent detection systems, providing a practical alternative to classical lock-in implementations for embedded applications.