Design and Implementation of an 8-Bit Logical Barrel Shifter Using Cadence Virtuoso and Xcelium in 45 nm CMOS Technology

Shifting operations are fundamental to arithmetic and logic units in modern digital systems; however, conventional shift registers perform multi-bit shifts sequentially, leading to increased latency and reduced throughput. To overcome this limitation, barrel shifters are commonly em ployed to achieve single-cycle shifting using combinational logic, though detailed transistor-level implementations and verification are not always presented in academic works. In this paper, an 8-bit logical right barrel shifter is designed using a multiplexer-based static CMOS architecture and implemented at the transistor level using Cadence Virtuoso in 45-nm CMOS technology. The proposed design employs three cascaded stages corre- sponding to conditional shifts of 4, 2, and 1 bits, realized using a total of 24 static CMOS 2:1 multiplexers. Transistor-level verification is performed using Cadence Virtuoso, while functional correctness is validated through a Verilog testbench using Cadence Xcelium. Simulation results confirm correct logical right shift operation with full voltage swing and single-cycle performance at a supply voltage of 1.8 V, demonstrating the suitability of the proposed design for integration into processor and DSP architectures.