Digital Emulation of p-bits on FPGA-Based Embedded Systems for Spin-Inspired Probabilistic Logic

The exploration of probabilistic computing has recently gained momentum as a promising par-adigm to overcome the limitations of deterministic CMOS logic. In this paper, we present an FPGA-based digital emulator of probabilistic bits (p-bits) and stochastic logic circuits introducing three key innovations. First, we implement p-bits with a sigmoidal activation function, enabling faithful emulation of spin-inspired probabilistic logic while preserving the statistical character-istics of physical p-bit devices. Second, we eliminate the need for the sequencer—commonly re-quired in weighted p-bit architectures to sequentially activate each unit and ensure stability—by demonstrating, through quantitative metrics that our fully parallel design achieves stable and reproducible behavior. Third, we propose a reusable and parameterized hardware library of elementary probabilistic components, implemented as modular Verilog HDL blocks that provide a robust foundation for the construction of more complex stochastic systems, including Boltzmann machines, probabilistic SAT solvers, stochastic optimization architectures, and binary neural networks. With the proposed approach, we designed and emulated on Altera/Intel FPGAs using the Quartus Prime Integrated Development Environment (IDE) a wide set of probabilistic logic gates and probabilistic digital systems up to finite state machines (FSMs), achieving excellent results in terms of both accuracy and stability of the outcomes. The proposed FPGA-based archi-tecture thus serves both as a research instrument for investigating probabilistic computation and as a practical platform for scalable hardware accelerators in emerging stochastic applications.