Error-Resilient Quantum Circuit Design of Hybrid Approximate-Exact 5:2 Compressors for Arithmetic Applications

This work presents a resource-efficient architecture for quantum 5:2 compressors, addressing the prohibitively high T-count and circuit depth of exact arithmetic in the Noisy Intermediate-Scale Quantum (NISQ) regime. We implement a Hybrid Approximate-Exact synthesis methodology that fundamentally alters the logic synthesis path to prioritize quantum cost over strict logical equivalence. The proposed design intentionally isolates and excludes the fourth input bit (í µí±¥ 4)from the critical carry computation path during the initial approximation stage, significantly pruning the required Toffoli gate count. To mitigate the induced error, the proposed approach integrate a dedicated Error Correction Module (ECM) based on half-adder logic that realigns the significance weights of the intermediate sum and carry vectors. Validation via Qiskit Aer exhaustive statevector simulation confirms that this architecture achieves a superior Pareto frontier between circuit fidelity and arithmetic precision compared to fully exact baselines. The resulting topology minimizes decoherence-induced errors by reducing the gate depth, providing a viable arithmetic primitive for error-tolerant quantum algorithms.