The Quantum DIMM: A Coaxial 3D-Stacked Architecture for Scalable Silicon Quantum Computing

The scalability of silicon-based quantum computers is fundamentally limited by the electromagnetic density of control interfaces—the “Wiring Wall.” While recent breakthroughs have demonstrated high-fidelity spin qubit operation at temperatures above 1 K [22], enabling the co-integration of qubits with cryo-CMOS logic, the geometry of 2D planar architectures remains a bottleneck for megabyte-scale integration. We present the “Quantum DIMM,” a 3D-stacked architecture that leverages standard commercial Through-Silicon Vias (TSVs) to vertically integrate control electronics directly beneath the qubit layer. Using a multi-physics simulation framework, we demonstrate that a 10 µm amorphous SiO2 interposer acts as a thermal “one-way valve” (κSi/κSiO2 ≈ 6000), maintaining qubit temperatures within 1.3 mK of the heat sink even under 5 W of active power dissipation. Furthermore, we show that by optimizing the TSV geometry for 50 Ω impedance matching, the grounded coaxial shell suppresses electromagnetic crosstalk by-140 dB. Integrating the dominant magnetic flux noise from surface spins (mitigated by α-Si passivation), this architecture achieves a robust coherence time of T2 ≈ 68.2 ms for 31P nuclear spins, combining the manufacturability of 3D-stacked memory with the coherence required for fault-tolerant quantum computing.