Resolving the Thermal Bottleneck in 3D-ICs: A Ramanujan-Bhabha Quantum-Thermal Framework for Next-Gen VLSI

The aggressive scaling of semiconductor devices into the sub-10nm and Angstrom regimes has rendered classical Fourier-based heat diffusion models obsolete. In 3D Integrated Circuits (3D-ICs), vertical stacking creates a “Thermal Trap” where phonons behave ballistically rather than diffusively. This paper introduces a novel framework synthesizing Homi Bhabha’s Cascade Physics and Srinivasa Ramanujan’s Mock Theta Functions to predict internal silicon temperatures. We demonstrate that at the 9nm node, industry tools underestimate junction temperatures by as much as _{48 . 5} ^◦ C. By deriving Effective Thermal Conductivity ( _keff ) via Mellin Transforms and Knudsen scaling, we establish a rigorous calculation methodology. Our results, verified against hardware-level simulation, enable “Thermal-Aware” design for 3nm and 2nm architectures, bridging the gap between macroscopic simulation and quantum-thermal reality.