Chip-level voltage controlled magnetic p-bits array with variation compensation for stochastic neural network computation

The increasing computational and energy-efficiency demands of artificial intelligence are driving the development of in-memory computing based on emerging memory devices. Probabilistic bits (p-bits) based on magnetic tunnel junction (MTJ), benefiting from non-volatility, CMOS compatibility, and fast sampling, show broad potential in stochastic neural networks. However, unavoidable device-to-device variations in MTJ switching probabilities hiders the realization of scalable p-bit chips. Here, we integrate a high-density array of voltage-controlled magnetic anisotropy MTJs (VCMA-MTJs) and employ a tail truncation strategy to compensate for their variations in probabilistic switching ranges, enabling chip-level p-bit functionality. Our VCMA-MTJ chip (VM-chip) successfully implements restricted Boltzmann machines (RBM) and deep belief network (DBN) for image recognition, anomaly detection, image completion, and image generation, demonstrating the practical utility of this chip in stochastic neural networks. Furthermore, we propose a dual-control strategy that tunes both the amplitude and duration of the voltage pulse, significantly enhancing network performance and surpassing the results obtained using conventional software-generated pseudo-random number. Our work enhances the system tolerance to variations in MTJ switching probabilities, thereby reducing manufacturing costs and facilitating large-scale production, ultimately accelerating the chip-level hardware deployment of p-bits in artificial intelligence applications.