Ultra-Fast Ising Machine for Combinatorial Optimization using Sub-nanosecond CMOS-integrated Magnetoresistive Random Access Memory

Physics-inspired Ising machines are emerging as promising hardware alternatives to traditional von Neumann architectures for tackling computationally intensive combinatorial optimization problems (COPs). However, the practical application of existing quantum, optical, and electronic platforms is fundamentally constrained in speed and scalability by the physical mechanisms governing their spin dynamics. Here, we report, to our knowledge, the first complementary metal-oxide-semiconductor-integrated chip-scale spintronic Ising machine that enables sub-nanosecond probabilistic spin updates. Exploiting the voltage-controlled magnetic anisotropy effect in dense magnetoresistive random access memory, our design eliminates large write currents and achieves a tunable 0-100% single-pulse switching probability via pulse-width control. Compared with prior spintronic implementations, it achieves a simultaneous 100× improvement in spin-update speed (0.3-1 ns) and energy efficiency (< 40 fJ). Leveraging the all-to-all Ising machine implemented on-chip, we validate its generality on industry-relevant COPs in the electronic design automation domain, including global routing and layer assignment, attaining high-quality solutions with a system energy efficiency of 2.5×104 solutions per second per watt. This performance outperforms state-of-the-art quantum and graphics processing units by six and seven orders of magnitude on identical benchmarks, respectively. Our results open the sub-nanosecond regime of probabilistic spin updates in a chip-scale Ising machine, establishing spintronics as a compelling route for ultra-fast and scalable physics-inspired intelligence.