A design of SP6T and SP8T RF switch chips with high isolation and low insertion loss based on SOI CMOS technology

A high-performance RF(Radio Frequency) switch chip integrating a CMOS front-end control driver module is designed in this paper based on the 0.11µm SOI CMOS process. This chip integrates the SP6T and SP8T switches for the first time, and the two switches operate in different frequency bands respectively. This RF switch chip is designed for use in RF front-end transceiver systems, mainly for channel selection at the receiving end (Rx). Meanwhile, a series-parallel structure design is adopted by the chip, and the overall performance is further enhanced through negative pressure bias technology. The SP6T switch in this chip operates in the Low-Band frequency band below 0.9GHz. The insertion loss is 0.44dB, the isolation is 38.22-47.60dB, the input P0.1dB compression point is 30.61dBm, the second harmonic is 97.12dBm, and the third harmonic is 99.73dBm. The switch switching time is 200.89ns. The SP8T switch in this chip operates in the High-Band frequency band below 2.7GHz and also takes into account the Mid-Band frequency band below 2GHz. The insertion loss is 0.90dB, the isolation is 30.82-34.95dB, and the input P0.1dB compression point is 33.65dBm. The second harmonic is 93.77dBm, the third harmonic is 95.49dBm, the switching time is 205.55ns, and the current consumption of the CMOS front-end control drive module is approximately 100µA. The size of the proposed RF switch chip is 730µm×730µm.