An Area-Efficient High-Q Adjacent Stack Zigzag-Polygonal On- Chip Inductor Using Customized Metal Stacking in TSMC 180-nm Technology

On-chip inductors implemented using regular metal stacking generally suffer fromlow inductance and poor quality factor at millimeter-wave frequencies. In this work,a zigzag polygonal inductor is proposed by adding a metal layer in parallel with theexisting metal stack of TSMC 180nm technology, which results in an increase of 43%and 155% in inductance and Q-factor, respectively. To further increase the inductanceperformance, an adjacent stacked configuration is proposed where the bottom inductoris placed adjacent to the top inductor. This configuration reduces the parasiticcapacitance, resulting in improved Q and L. The adjacent stack zigzag polygonalinductor achieves a 3.78-times increase in inductance and 8.3% increase in Q over thezigzag polygonal inductor with a 4.6% area overhead at 30 GHz. The proposedinductor, when compared to the recent designs, gives better Q with a significantlycompact footprint. To validate the performance of the inductor, an LC band-pass filter(BPF) is designed, yielding an insertion loss of 0.35 dB and a noise figure of 0.33 dB.When compared to the recent works, this filter gives better performance with highcompactness in the on-chip area. These results validate that the proposed inductor isa viable and area-efficient solution for space-constrained, high-frequency 5G RFfront-ends.