On-chip Scalable High-speed Active Battery Balancer

Fast active battery balancing circuits often suffer from high implementation cost and limited performance due to the large number of required power switches, gate drivers, and sensing circuitry. Moreover, their balancing speed and efficiency are constrained by parasitic resistances and inductances, resulting in bulky designs and poor scalability. This paper presents a high-speed on-chip active battery balancing module based on flexible stacked half-bridge submodules capable of interfacing with multiple off-chip capacitor networks. The proposed architecture is driven by a single control signal and operates autonomously, eliminating the need for voltage or current sensor-based balancing algorithms. The chip natively supports balancing among four battery cells and can be readily extended to larger battery strings. All control functions, including dead-time generation, voltage level shifting, and gate driving of the balancing switches, are fully integrated on a 3.4 mm2 die fabricated in a 130-nm Bipolar-CMOS-DMOS (BCD) process using 5-V lateral power switches. To validate the balancing capability, the chip is connected to four external balancing capacitors arranged in a star configuration, and a full-bridge configuration is realized using an additional chip to enhance performance. Experimental results demonstrate robust operation over a wide range of conditions, with switching frequencies from 1 kHz to 5 MHz and cell voltages from 2.4 V to 4.3 V. The proposed circuit achieves effective battery balancing with an average balancing current of up to 2.5 A