Combined True Time Delay System Based on Inductor- less CMOS True-Time-Delay Cell

A novel true-time delay (TTD) system for 1-5GHz applications is presented in this paper. Conventional TTD systems must be better optimized in low frequencies. Most existing structures use transmission lines (TLs), artificial transmission lines (ATLs), or LC ladder structures, which result in large chip areas due to the size of the inductors. Some systems employ two different delay cells in their topologies, which is not desired for integration purposes. To address these issues, a combined true-time delay cell system (CTTDS) is proposed. This system consists of N-semi-identical building blocks, which can be cascaded to provide sufficient delay. Each block includes nearly identical TTD cells. A 4-bit resolution delay system with a 14 ps delay step and a total delay of 210 ps demonstrates the concept. The delay cells are inverter-based, inductor-less designs with resistive feedback to ensure wideband operation. Single pole dual throw (SPDT) switches are used to select the proper path for each cell in the system. This design is designed in TSMC 180nm CMOS technology.