Design and implementation of CSVCO for PLL applications

This paper depicts the design and performance analysis of Current Starved Voltage Controlled Oscillator (CSVCO), With different low leakage power techniques. This low power techniques of CSVCO is implemented in Phase Locked Loop by achiving the various field of applications, which are suitable to show efficient result of PLL for fast locking system, such as Frequency synthesizer, Multiplier and Frequency control, Tracking generators, Clock generation and recovery system etc. The proposed work sleep stack technique CSVCO which consumes low power, Less Area, Low Phase Noise, Less Delay, Also achieving higher frequency tuning range. Low power consumption gives significantly higher efficiency of PLL. This CSVCO simulation work is performed about the parameters of the phase noise is -63.8 dBc/Hz with supply voltage 0.45V and frequency of 2.759GHz. Power (mw) 0.002559, Delay(µs) 0.0006544. Complete work done by using cadence virtuoso 45NM CMOS technology.