Design and Simulation of High Gain LNA Using 28nm Technology

This research paper details the development of a cutting-edge Low Noise Amplifier (LNA) using advanced 28nm (TSMC) CMOS technology. The study focuses on achieving optimal performance in high-frequency wireless communication systems. The LNA design showcases a significant gain of 40.39 dB at 6.31 GHz and an impressive noise figure of 6.68 dB at 6.31 GHz. The methodology includes the utilization of a common-source stage LNA configuration with inductive source degeneration and cascade structures to enhance gain and noise performance. Special emphasis was placed on impedance matching, with a meticulous design of input and output networks to minimize signal loss and noise addition. The paper also explores key aspects of LNA design such as transistor sizing, stability, and linearity. Stability is rigorously analyzed using S-parameters, ensuring the LNA’s resistance to self-oscillations.