Design of stable low leakage Power Optimized SRAM Array

This paper presents the design and comprehensive analysis of a low-power 2X2 SRAM array using CMOS 90nm technology. The proposed system is targeting energy constrained applications such as mobile and embedded systems. The implemented SRAM architecture incorporates a 10T with stacking cell, optimized word line and bit line schemes, and efficient row and column decoders. Robust read and write functionalities are ensured through the integration of precharge circuits, a differential sense amplifier, and write drivers. To minimize power dissipation, transistor stacking techniques are strategically employed within the memory array. The performance of the designed SRAM is rigorously evaluated through simulations using Cadence Virtuoso and Spectre, focusing on critical parameters including hold stability, read stability, write margin, and power consumption. The simulation results demonstrate significant enhancements in power efficiency, read access time, and noise immunity, highlighting the suitability of this SRAM design for energy-efficient systems.