ASIC Design of Area Efficient Analog Frontend for Image Sharpening Applications

In this research article we propose a new analog sharpening filter analog frontend (SAF) for image enhancement. The SAF is built using a bulk-controlled datum pair (BC-DP), enabling threshold equalization between amplifying and load MOSFETs and achieving better linearization in the processed output signal. The reported SAF incorporates a differential weight mask to achieve bias currents in cascaded BC-DPs. To process the 3×3 kernel of the input image, the proposed SAF utilizes nine BC-DP cells connected in parallel. The parallel operation of BC-DP cells achieves better processing speed compared to their digital counterparts, which employ adders and multipliers to realize the filter structure whose processing capability is bottlenecked by the carry propagation delay of adder units. Furthermore, to achieve area efficiency, we omit the corner pixels in the input kernel for processing, and the truncated version of the SAF (SAFTrun) is realized using five BC-DP cells. Simulations reveal that the reported SAF and its truncated version are able to achieve better operating frequencies when compared to the few other AFEs proposed for image processing applications. Semi-Conductor Laboratory (SCL) 180nm MOSFETs are used to implement the reported SAFs.