A Wide Tuning Range High Performance PLL Based on Capacitor Arrays

The paper presents a wide tuning range high performance PLL, which is mainly used for high speed wideband clock signal generation to reduce the difficulty of providing high-speed input clocks externally. The circuit mainly consists of PFD, CP, VCO, DIVIDER and other units. It improves the phase noise of the VCO by reducing the VCO tuning gain, and uses a capacitor array to extend the output frequency range. The circuit is designed in a 28nm process and the output signals can work from 8GHz to 12GHz. The PLL is used as a sampling clock for the DAC. When the DAC outputs a 1.8GHz sine wave, the measured phase noise can reach -110dBc/Hz@100kHz offset.