Instruction Set Optimization for FM-Type Digital Signal Processor (DSP) Architectures with Integration of DVB-T2 TV Systems

The computational demands of DVB-T2 (Digital Video Broadcasting – Second Generation Terrestrial) systems require highly efficient baseband processing architectures capable of real-time execution under strict power and latency constraints. DVB-T2 supports FFT sizes up to 32K carriers, modulation schemes up to 256-QAM, code rates ranging from 1/2 to 5/6, and channel bandwidths of 6–8 MHz, resulting in payload bitrates exceeding 40 Mbps per multiplex. Core receiver operations including OFDM demodulation, LDPC decoding (block lengths up to 64,800 bits), channel estimation, and time–frequency interleaving are computationally intensive and dominated by multiply-accumulate (MAC) operations. This work investigates instruction set optimization for FM-type fixed-point DSP architectures to accelerate DVB-T2 physical layer processing. Architectural enhancements such as SIMD-based complex MAC instructions, fused multiply-add (FMA) operations, bit-reversed addressing, zero-overhead looping, and saturation arithmetic are proposed to reduce execution cycles and memory latency. The results demonstrate that application-specific instruction set customization significantly enhances throughput, energy efficiency, and silicon utilization in embedded DVB-T2 TV receivers and software-defined radio platforms.