A Generalized SMCF-Driven Adaptive Test Framework for Pre-Silicon Verification of On-Chip Sensors with Formal and Stochastic Modeling

Emerging sub-7 nm systems-on-chip (SoCs) dissipate power densities exceeding 1 W mm⁻², leaving only a narrow thermal guard-band before devices cross their safe-operating limits. ARM’s System Monitoring and Control Framework (SMCF) unifies access to on-chip monitors through a single register map, yet production-grade verification of the sensors themselves remains largely manual and occurs late in the development life-cycle. This paper presents a self-checking, SMCF-driven automated test engine that validates a ring-oscillator temperature sensor entirely within an ARM Fast Models virtual platform prior to first silicon. To enhance analytical rigor, we incorporate formal modeling of thermal noise and sensor drift using a stochastic simulation framework, providing insight into system stability under statistical variance. The architecture further generalizes to support other sensor types—such as voltage droop or current monitors—through a sensor-agnostic LISA+ specification and test engine interface. A novel adaptive test pattern generation strategy is introduced, using functional coverage metrics and statistical predictions to dynamically prioritize stimulus and maximize validation efficiency. Additionally, an AI-guided coverage estimator is embedded for predictive validation feedback. The C + + testbench consumes LISA-generated register definitions, drives enable and reset clocks over PV Bus, and exhaustively sweeps the frequency-to-temperature (F↔T) golden table with ± 1% accuracy. A Robot Framework layer publishes every check as a keyword, enabling readable scripts, interactive HTML dashboards, and seamless Jenkins continuous-integration hooks. Initial experiments achieve 100% functional coverage in less than 90 s of wall-clock run-time, while capturing edge-case thermal violations and maximizing pre-silicon validation throughput.