Development of Bifurcation Prediction and Process Emulation for Warpage Prediction in Fan-out Wafer Level Packaging Based on Material Equivalence

Fan-out wafer level packages (FOWLP) have been widely used in IC packaging industries but the associated asymmetric warpage in the process may affect the process integrity and final product yields. Such a concern should be reduced through proper design based on adequate analysis and efficient and process simulation. The full-scale FEM simulations, although accurate, is inadequate for early-stage design analysis due to high computational cost. In this work, essential semi-analytical models for bifurcation prediction and efficient process emulators are developed to fully address the needs by modeling a comprehensive reconstituted wafer as a bi-layer-equivalent anisotropic structure for estimating key performances index such as bifurcation temperatures and processing warpages. Various material equivalence models are compared and their effectiveness and accuracy have been evaluated and the virtual tensile testing approach is finally adapted. In comparison with the corresponding fully 3D FEM, the simplified model shows that a slight sacrifice on the achieved accuracy could reduce computational cost significantly based on the same hardware and this implies that a more thoughtful software DOE could be conducted for optimization. Subsequently, the standard chip-first and chip-last process emulators are then developed for predicting the wafer warping behavior throughout the entire processing and to perform parametric study to elucidate the applications of this work in packaging design analysis.