Dynamic Key Generation With LSTM: A Robust Defence Against DPA Attacks on FPGA-based AES Cryptosystems

This research presents a new, hardware-efficient cryptosystem that integrates a Long Short-Term Memory (LSTM) network with the Advanced Encryption Standard (AES) on an FPGA to create a strong first line of defense against Differential Power Analysis (DPA) attacks. The key innovation is a dynamic key generation scheme that uses an on-chip NIOS II processor to run a pre-trained LSTM model to create non-deterministic, session-specific round keys in real-time, breaking the statistical relationships that side-channel attackers exploit to create their attacks. The system is implemented in a Cyclone IV DE2-115 FPGA, and was thoroughly tested using functional simulation and physical synthesis. The architecture has an impressive throughput of 989.94 Mbps, at a maximum clock speed of 400.198 MHz, indicating that it is possible to have a high level of security without sacrificing performance. The comprehensive side-channel analysis, including correlation power analysis and Test Vector Leakage Assessment (TVLA) t-tests, has validated that there is nothing that can be used to create DPA attacks, showing that there was no usable leakage of data after > 100,000 power traces were recorded. The consumption of 12.5% of slice registers and 14.5% of LUTs, although a burden for the design to include the neural key scheduler and soft-core processor, is justified, and the dynamic power consumption of the design is only 0.5 mW. Thus, this work provides a new direction for designing DPA-resistant cryptographic accelerators, proving that the use of machine learning-generated dynamic keys can significantly increase the security of these systems.