A Lightweight Hardware Encryption System Featuring an Efficient Tower Field S-Box Scheme

Lightweight encryption algorithms provide effective protection for data security in resource-constrained hardware devices. The S-box plays a crucial role in the lightweight implementation of the encryption algorithm. However, balancing area, delay, and security in the implementation of the S-box remains a challenging task. In this paper, we propose an efficient S-box design that integrates a compact combinational logic architecture with a tower field masking-based secure scheme. First, we propose a transformation matrix expansion mechanism for the S-box; then, we present a $k$-node bundled search strategy with a maximum depth constraint to solve the expansion matrix. Second, we propose a sub-module series connection method, which utilizes a backtracking judgment mechanism to reduce circuit depth. Third, we propose a tower field masking reuse scheme based on correction term computation to enhance security. Finally, we present the SM4 algorithm implementation and encryption system evaluation. Our design optimizes and balances both compact and secure, the design achieves a reduced circuit area and a lower logic depth. Furthermore, the encryption system demonstrates lower resource utilization, decreased energy consumption, and strong resistance against side-channel attacks.