Unifying Heterogeneous and Monolithic Integration via Dual-sided 3D Technology

Artificial Intelligence (AI), has been occupying the central position in recent technological advancement, propelled by exponentially increasing computing resources, which in turn stimulate the demand on higher level 3D integration for integrated circuits. However, current frontside-only integration is inevitably bottlenecked by the routing congestion and parasitic degradation on the wafer frontside, blocking the further down scaling. Fortunately, the underutilized backside space of wafer provides inimitable opportunities to break this blockage. Here, we demonstrate the "Flip 3D" (F3D) technology which utilizes both sides of wafer to capture the ultra-high-density connectivity of monolithic integration while maintaining the architectural flexibility of heterogeneous integration. F3D technology enables the co-integration of logic, memory, and connectivity with significantly reduced interconnect parasitics. Experimentally, F3D technology was verified on a FinFET test vehicle in a dual-sided form, successfully integrating logic, temperature sensors, optical modules, on-chip memory, and high-density computing-in-memory cells. We further introduce "Hyper 3D" (H3D) technology for dual-sided system-on-wafer integration. Our results validate that this unified dual-sided scheme provides effective solution to the "computing," "memory," and "connectivity" walls. This work establishes a scalable roadmap for multi-layer on-chip systems, providing a full-3D hardware strategy for the next generation of AI hardware.