Stabilizing SrVO₃ Bottom Electrodes for High k SrTiO₃ Integration via La Doped STO Passivation and O₃ Reduced Atomic Layer Deposition

The increasing demand for higher capacitance density in dynamic random-access memory (DRAM) has driven the need to integrate high- k dielectric materials. SrTiO ₃ (STO) has emerged as a promising candidate owing to its high dielectric constant of over 100 in thin-film form. To achieve a high dielectric constant for STO, it is crucial to select bottom electrode materials with superior lattice matching with STO. This study evaluates the potential of SrVO ₃ (SVO) electrodes used with atomic layer deposition (ALD) STO, thereby addressing the challenges associated with the stability of SVO during the ALD STO process. The results indicate that applying La:STO oxygen-blocking layers effectively mitigates SVO degradation during the ALD process. Furthermore, reducing the O ₃ concentration during ALD enabled the successful integration of high-quality STO on SVO with a bulk dielectric constant of 175 and exceptionally well-maintained interfacial properties. This study evaluates SVO as a promising electrode candidate for utilizing STO in next-generation DRAM and demonstrates its potential to provide increased capacitance density and reduced leakage currents.