TiO2 Nanolayer-Assisted Top-Interface Engineering for Disturbance-Free FeFETs: A Blueprint for Future van der Waals Memory

Metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si (MIFIS) ferroelectric field-effect transistors (FeFETs) are attractive for large memory window (MW) and low-voltage FE NAND operation. Nevertheless, its fundamental operating principle also makes the device vulnerable to threshold voltage (V _th ) shift under repeated disturb bias, which remains a major obstacle to array-level reliability. In this study, we employ a TiO ₂ nanolayer (NL) at the upper interface of the HZO FE layer to address this issue while preserving the low-voltage advantage of the MIFIS structure. The inserted TiO ₂ modifies the interfacial electrostatics and the ferroelectric switching characteristics at the same time. First, owing to its high dielectric constant and band alignment, it facilitates additional gate-side charge storage near the G.IL/FE interface. Second, it alters the switching nature of the underlying HZO toward a more abrupt response associated with enlarged effective domain size and improved remanent polarization. The proposed device with TiO ₂ NL operates below 15 V, while maintaining a large MW of 7.57 V, which is 18.9% higher than the reference device. Notably, the proposed device remains disturbance-free even after 10 ⁵ cycles of 9 V/10 µs disturbance stress, whereas the counterpart experiences severe disturbance under the same conditions. Thus, we clarify that partial P switching acts as the primary driver of disturbances, as it precedes charge trapping and accelerates gate charge injection. Finally, while our top-interface engineering successfully optimizes gate-side dynamics, we propose that replacing the Si channel and bottom interlayer with emerging van der Waals (vdW) semiconductors and 2D insulators (e.g., h-BN) can fundamentally suppress channel-side charge injection (Q _it ). Combining this vdW-based bottom-interface with our TiO ₂ top-interface strategy presents a comprehensive blueprint to expand the MW and realize ultimate disturbance-free operation in next-generation computing architectures.