Modular FPGA Design for Montgomery Multiplication Using MATLAB HDL Coder

FPGAs have become vital tools in the design, implementation, and testing of computing algorithms. This paper aims to investigate the impact of the MATLAB HDL Coder script writing method on its synthesis to FPGA resources. This is achieved by designing a complex computational algorithm in a modular way. Three necessary modules are the memory module, the control module, and the computation module, which are analyzed as independent MATLAB HDL coder projects. This analysis includes examining the synthesis report for each module and evaluating them collectively. The modular, scalable design of the Montgomery multiplier Algorithm enables studying area consumption and speed in a combined manner. The analysis shows that the control module has less effect on the speed and the area. The memory module is very fast but shares the area with the computation module. The main module that affects the speed is the computation module. The target platform is xc7vx330t-2ffg1157 Virtex-7 Xilinx FPGA.