Adaptive Fault Resilience Techniques for Flash Memory Used in DNN Accelerators

Deep neural networks (DNNs) are increasingly utilized in various applications, including smart appliances, facial recognition, and autonomous driving. The weight data generated during training are typically stored in flash memory, which is prone to reliability and endurance challenges. Given the inherent error tolerance of DNN applications, adaptive fault resilience techniques have been proposed to safeguard the weight data stored in flash memory. Initially, an analysis of bit significance is conducted to ascertain the priority of weight bits that require protection. Subsequently, a novel weight transposer and an address remapper are introduced to reallocate significant weight bits to more reliable or fault-free flash memory cells. A bipartite graph model is developed to facilitate the modeling of address remapping and the assessment of error scores. Additionally, corresponding hardware architectures for address remapping are proposed. The deep learning framework PyTorch is employed to evaluate inference accuracy across various DNN models. Experimental results indicate that, with an injected bit error rate (BER) of 0.01% in the weight data, the accuracy losses for commonly used DNN models remain below 1%, accompanied by negligible hardware overhead.