Variability in 2D Field Effect Transistors

As silicon-based field-effect transistors (FETs) approach their scaling limits, two-dimensional (2D) semiconductors are emerging as strong contenders for next-generation nanoelectronics. A major barrier to their integration, however, is device-to-device variability that undermines circuit reliability. Here, we present a systematic study linking variability in 2D FETs to both material growth and dielectric integration. Using six distinct metal organic chemical vapor deposition (MOCVD) growth conditions, we systematically studied the impact of epitaxy, grain boundary, and bilayer island coverage on electrical uniformity. We further examine four gate dielectrics: HfO2, Al2O3, ZrO2, and AlN, highlighting the role of dielectric-induced interface roughness in exacerbating variability. Our analysis separates long-range variations from micron-scale fluctuations, revealing that MoS2 exhibits substantially lower variability than WSe2, which remains strongly inhomogeneous even at short length scales. Notably, our HfO2-gated MoS2 FETs, featuring ~1 nm equivalent oxide thickness (EOT) achieve a Pelgrom slope of 7.5 mV-µm, approaching the silicon benchmark of 2.8 mV-µm. These devices also deliver an on-state current up to 300 µA/µm, subthreshold swing as low as 73 mV/dec for 35 nm channel lengths, and a record high mobility of 120 cm2/V-s in long-channel devices. These results demonstrate that variability mitigation can be achieved without compromising performance, and to our knowledge, represents the first statistical correlation of device level variability with both material growth parameters and dielectric choice. This work provides essential design and processing guidelines for scalable, high-performance, and reliable 2D electronics.