Device Modeling and Performance Analysis of FinFETs for Advanced Technology Nodes Using TCAD

The continuous scaling of complementary metal–oxide–semiconductor (CMOS) devices beyond the 10 nm technology node has rendered conventional planar transistors ineffective due to severe short-channel effects (SCEs), leakage currents, and variability. Fin field-effect transistors (FinFETs), with their multi-gate geometry and superior electrostatic control, have emerged as the mainstream solution in advanced nodes. In this work, a comprehensive device modeling and performance analysis of FinFETs is presented using Technology Computer-Aided Design (TCAD). The study incorporates detailed I–V and C–V characteristics extraction, followed by systematic analysis of critical performance metrics including threshold voltage (Vth), subthreshold swing (SS), drain-induced barrier lowering (DIBL), ON/OFF current ratio, transconductance (gm), and cutoff frequency (fT). Variability analysis considering random dopant fluctuations, line-edge roughness, and workfunction variations is also conducted, providing statistical insight into device reliability. Furthermore, compact models are developed and validated against TCAD results to enable integration into SPICE-level circuit simulations. Comparative benchmarking with emerging architectures such as nanosheet FETs (NSFETs) and complementary FETs (CFETs) demonstrates the performance–scaling trade-offs of FinFETs at sub-5 nm nodes. The results highlight that optimized FinFET designs achieve improved drive current and reduced leakage while maintaining manufacturability, thereby underscoring their continued relevance in the near future. This work contributes a rigorous TCAD-to-compact modeling workflow that bridges device-level physics with circuit-level performance evaluation, supporting the design of energy-efficient nanoscale CMOS technologies.