Floating-point matrix multiplication optimized through the integration of hybrid multiplier techniques

In order to support high power computing applications, we aimed to design a novel framework for floating point matrix multiplication. In the proposal of matrix multiplication processing elements (PEs), multipliers such as Strassen, Karatsuba and Vedic are utilized to maximize the architecture performance. The Urdhava Tiryabhyam sutra from the Vedic multiplier is one of them that decreases partial products in multiplication while simultaneously speeding up the process. This paper proposes the design of Strassen matrix multiplication algorithm with the combined features of Urdhava Tiryabhyam and Karatsuba multiplier. The Karatsuba algorithm is inefficient at lower orders of multiplication, but it works well at higher orders. Thus, at a lower level, the Urdhava Tiryabhyam Multiplier is applied. A floating-point matrix multiplication architecture was developed using Verilog HDL and implemented on the Virtex-5 FPGA – XC5VSX95T. The design was developed, verified through simulation, and implemented using Xilinx ISE 13.5.