Improved performance of Error Controlling Codes using novel XOR gates

Error correction codes (ECCs) are essential for maintaining data integrity in sophisticated digital systems, including System-on-Chip (SoC) architectures and Data Link Layer protocols. This work introduces a VLSI-optimized implementation of Hamming, Dual Rail, Checksum-XOR, and Two-Dimensional Parity with Duplication (2DPD) codes, highlighting their effectiveness in error detection and correction. The suggested method utilizes innovative XOR gate topologies realized in complementary metal-oxide-semiconductor (CMOS) technology to attain high-speed, low-power performance and improved throughput. The XOR gate implementation in Fig. 6(h) exhibits enhanced performance, attaining considerable increases in Power-Delay Product (PDP) efficiency. Hamming codes provide single-error rectification and double-error detection via strategic placement of parity bits, whereas Checksum-XOR improves error detection in protocols such as TCP and UDP. Dual Rail coding enhances fault tolerance in safety-critical System-on-Chip designs by utilizing signal redundancy, while 2DPD provides resilient error correction for memory arrays and specific network topologies. Experimental findings indicate that Fig. 6(h) attains PDP efficiency enhancements of up to 90.68% for Dual Rail and 90.56% for 2DPD codes relative to CMOS across 8-bit, 16-bit, and 32-bit configurations, demonstrating consistent superiority over other XOR gate designs depicted in Figs. 6(b), 6(e), and 6(i). Thorough trade-off evaluations of redundancy, computational complexity, and error-correction capacity substantiate the proposed designs, especially Fig. 6(h), as exceptionally appropriate for low-power, high-performance applications in contemporary digital systems.