Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders  for Quantum Error Correction Codes

Belief propagation (BP) combined with ordered statistics decoding (OSD) offers a good balance between accuracy and complexity for many quantum error correction (QEC) codes, making it nearly a universal decoder. However, the complexity of OSD can impose timing constraints on real-time decoding for certain quantum technologies, such as superconducting qubits. Recent experiments have demonstrated that larger time budgets are available for the decoding process. Nevertheless, the limits of classical hardware decoder implementations have not been explored. Therefore, the code distance boundaries for different code families that real-time decoders may support remain unknown. For this reason, it is essential to evaluate the architecture of OSD and explore its limits for code families, such as bicycle bivariate codes and surface codes, under realistic assumptions like the detector error model. The findings from this analysis will benefit not only superconducting qubits but also any quantum technology, as improvements will be advantageous when quantum systems scale up. This paper introduces a BP+OSD parallel architecture implemented in both FPGA and ASIC for various surface codes with distances from 3 to 21 and bicycle bivariate codes ranging from distances 6 to 24. Results indicate that decoders for surface codes can fit into a single VCU129 FPGA up to distance 9, achieving a maximum frequency of 200 MHz and a worst-case latency of 134 \(\mu s\) . For bicycle bivariate codes, the limits are found at distance 12, with a maximum frequency of 244 MHz and a worst-case latency of 84 $\mu s$. In ASIC technology using a 45nm process, the latency limits improve 31%, and area resources explode for the same code distances, making parallel implementation beyond distance 12 impractical in a single chip.The designs proposed in this work have been verified through a hardware emulator to ensure that the behavior of reference codes matches software simulations within a reasonable logical error rate. The behavior of lower regions, previously unexplored with software, has been examined using emulation down to \(10^{-12}\) , generating interesting results, such as changes in the decoder slope that suggest the emergence of an error floor when BP+OSD achieves low logical error rates.