Scalable and Energy-Efficient Peierls Transition Neuron for Monolithic Integrated Neural Network

While in-memory computing offers a promising approach to overcoming the limitations of the traditional von Neumann architecture, implementing an activation function, a critical component of neural networks, still requires substantial energy and area consumption when using conventional analog or digital circuitry. In this study, we introduce a two-terminal niobium-dioxide-based Peierls transition neuron (Peierls-neuron) that enables direct device-level implementation of the activation function. Through monolithic three-dimensional(3D) vertical integration of Peierls-neurons with synaptic devices, a highly compact neural network architecture is achieved featuring minimal interconnect overhead and maximum array density. A simple tuning method using a parallel resistor allows seamless compatibility with a broad range of synaptic conductance levels, thereby eliminating the need for additional peripheral circuits. Our integrated architecture achieves over 10 ⁴ times area reduction and up to 183.7 times energy savings compared with conventional activation function circuits. These results demonstrate a highly scalable and energy-efficient solution for the hardware implementation of neural network.