Scalable and Robust Multi-Bit Spintronic Synapses for Analog In-Memory Computing

The pursuit of high-performance and energy-efficient computing for data-intensive algorithms such as deep neural networks (DNN) opens up exciting opportunities for emerging non-volatile memories (NVM). Particularly, implementing such non-volatile memory units in crossbar arrays as weight matrix storage can provide highly parallel and efficient means of processing matrix-vector multiplications, providing synaptic functionality for the neuromorphic computing paradigm. While numerous memristive and phase-change device systems have been investigated for synaptic crossbar arrays, it remains challenging to provide robust and efficient device technology for multi-bit (analog) synapses. In this work, a multi-level spintronic device based on a magnetic tunnel junction (MTJ) device is proposed and studied. By integrating a standard MTJ free layer exchange coupled with a granular magnetic nanostructure, multiple near-continuous resistive states can be induced thanks to the distribution of the energy barrier among individual magnetic grains. Our simulation analysis demonstrated superior scalability with small variability compared to other means of multi-level devices. System-level simulation demonstrates that enabling 2-bit per cell MRAM crossbars leads up to 3.2x improvement in hardware efficiency while maintaining the inference accuracy.