Design of Universal gates using Junctionless TFET

This work presents the design and performance evaluation of universal logic gates implemented using Junctionless Tunnel Field-Effect Transistors (JLTFETs) with a 20-nm channel. The JLTFET device was modeled using Sentaurus TCAD. JLTFET-based universal gates are designed using the lookup table-based Verilog A code obtained from TCAD values of the device. Detailed simulations were conducted to evaluate power consumption and propagation delay. The results were compared against conventional MOSFET-based implementations to highlight the advantages and trade-offs of JLTFET technology.