Reconfigurable large-scale optoelectronic reservoir computing on programmable silicon photonic processor

The ever-growing demand for artificial intelligence (AI) acceleration has motivated research on novel photonic neuromorphic computation architectures, aiming for breakthroughs in computation speed and energy efficiency. Reservoir computing (RC), a hardware-friendly and training-efficient paradigm, has emerged as a compelling candidate. However, existing photonic RC systems, whether in time-multiplexed single-node implementations or passive parallel interconnections, suffer from fixed reservoir connections, which significantly constrain their adaptability and computational versatility across tasks. Here, we propose a reconfigurable optoelectronic RC system featuring a multi-physical node architecture, constructed on a large-scale programmable silicon photonic arithmetic computing engine. By integrating 64 physical nodes with tunable interconnect topology and connection density, the system allows flexible configuration of the reservoir layer tailored to specific computational demands. We further present a scalable deep RC architecture that expand the model complexity to over 600 reservoir neurons. Operating at up to 1 GHz with a per-cycle latency of 3 ns, the platform achieves a throughput of 8.19 TOPS and demonstrates robust performance across diverse tasks. Experimental validation confirms state-of-the-art performance including modulation-format identification with 99.8% accuracy over severely distorted optical channels, nonlinear equalization yielding a 0.61dB improvement in signal-quality factor compared with conventional digital post-equalization, and benchmark hand-written digit image classification of 96.7% accuracy. This work offers a scalable and reconfigurable solution for high-speed, task-adaptive neuromorphic computing, paving the way for practical deployment of photonic intelligence systems.