Design and Comparison of low power fault tolerant logic circuit using QCA nano Technology

Quantum Dot Cellular Automata (QCA) is a promising alternative to traditional CMOS technologies for future nanocomputing due to its potential for ultra-low power consumption and high-density integration. However, the practical implementation of QCA circuits is challenged by fabrication defects, environmental noise, and the need for fault tolerance, particularly in larger-scale systems. This work examines various defects that may arise in majority gates and subsequently presents a comparative analysis of fault-tolerant majority gates, considering the number of device cells, types of defects, and levels of fault tolerance achieved. QCA Circuits are simulated on the QCA Designer tool version 2.0.3. This paper concentrates on the examination of single and double missing cell defects. The proposed majority gate is analyzed for single and double missing cell defects and also the the full adder is designed using the proposed MG.