Optimisation of Area, power and Subsequent Parameters of Multiplexers in Quantum Cell Automata Technology

A great alternative to CMOS circuit is Quantum Cellular Automata (QCA) technology. One of the essential digital logic circuit is multiplexer which has been designed and presented in our paper in a very efficient manner. Multiplexers commonly used in memory elements, ALU, registers and even in Boolean function realisations in simplest form. After a tremendous literature survey we have optimised the circuit of multiplexer to a simplest one. Previous researchers have designed 4:1 multiplexer using lowest 37 no of QCA cells. In respect to that we have reduced the QCA cell number to only 30 which is working with expected result. Scaling down of cell number will leads to reduction of area, delay, power consumption etc. Here we have achieved 60% reduction in area by the proposed 4:1 multiplexer compared to previous work. Consequently 76.7% reduction in power has been possible in our work which is most significant.