A Dynamic Overlap-contention-free Double-edge-triggered D-type Flip-flop with High Energy Efficiency

Considering the general trade-off between high-speed operation and low power consumption in digital integrated circuits, simultaneous reduction of the propagation delay and power dissipation in bistable memory elements represents a challenging task. A compact, dynamic, D-type double-edge-triggered flip-flop (DETFF) designed in a nanometer CMOS technology is presented. The proposed topology employs a 2:1 multiplexer to combine a pair of dynamic single-edge-triggered flip-flops, one of which is triggered on the rising edge and the other on the falling edge of a true single-phase clock (TSPC), thereby providing immunity to clock overlap contention hazards. The dynamic implementation accounts for the high-speed performance, and the use of only eight clocked transistors accounts for the low power operation of the proposed DETFF. Notably, operating with a 1-volt power supply at a clock frequency of 10 GHz, given a switching activity of 10%, the proposed DETFF exhibits an average Clock-to-Q delay of 59 psec and consumes 211 µW in a 90nm CMOS technology. A methodology based on CMOS lateral scaling rules is advanced to enable a fair comparison of the performance of the proposed topology with those of other high-performance designs. The proposed TSPC DETFF demonstrates the potential to outperform static designs in terms of speed and energy efficiency. Specifically, the proposed dynamic TSPC DETFF exhibits a lower clock-to-Q delay, and a lower power delay product than all the static low-power designs considered for comparison.