Hybrid CMOS circuits with 2D transistors: Projected performance down to sub-1 nm technology nodes

N-type field-effect transistor (FET) based on molybdenum disulfide (MoS ₂ ) demonstrate superior performance compared to Si transistor at extremely small sizes. However, their integration into CMOS circuits remains relatively underexplored. In this work, covering technology nodes ranging from 16 nm to 0.7 nm, we propose a MoS ₂ nFET and Si pFET (MoS ₂ /Si) hybrid CMOS architecture based on advanced Si CMOS technology, and comprehensively investigate the circuit-level performance. Guided by multi-scale experimental data, we calibrated the MoS₂ nFET model and validated it in devices with channel lengths down to 60 nm. The hybrid CMOS model combines scalable MoS ₂ nFET with Si pFETs, meeting International Roadmap for Devices and Systems (IRDS) specifications. Additionally, device structure, layout design rules, and interconnect parameters for different technology nodes are also considered. The results reveal that, due to the lower gate capacitance and superior off-state performance of MoS ₂ nFET, the MoS ₂ /Si hybrid CMOS architecture achieves a reduction of over 53% in circuit power at 1 nm and 0.7 nm nodes. The study also highlights that the junction-less characteristics of MoS ₂ nFETs provide further potential for scaling down layout area, while mitigating the negative effects of interconnects. Compared to Si CMOS architecture, the MoS ₂ /Si hybrid CMOS architecture shows a comprehensive improvement of 71% and 65% in performance, power, and area (PPA) triangle at 1 nm and 0.7 nm nodes, respectively. The introduction of 2D materials into hybrid CMOS technology is expected to break the performance bottleneck of Si CMOS technology in future higher-performance, lower-power integrated circuits.