Source / Drain Height Optimization in Trench Gate Nanosheet FETs for Reduced Off-State Current

Nanosheet field-effect transistors (NS FETs) have been introduced as cutting-edge technology in the foundry business. The NS FETs exhibit superior gate controllability and output current compared to conventional Fin FETs. However, NS FETs face challenges due to the presence of substrate parasitic n-type metal-oxide-semiconductor (NMOS), which increases off-state current ( I _OFF ) and impacts overall device reliability. In this context, trench gate (TG) NS FETs have been proposed as a solution, but the process for source/drain (S/D) formation in TG NS FETs remains unclear. This study focuses on optimizing the junction depth ( X _j ) in TG NS FETs, which is a key factor in enhancing device performance. A shallow X _j increases the effective gate length ( L _G.EFF ) of the substrate parasitic NMOS, effectively suppressing short-channel effects (SCEs). Both device fabrication and electrical characteristics are simulated using 3-dimensional (3-D) technology computer-aided design (TCAD), with various design parameters considered, to guide the development of TG NS FETs.