A Capacitance Based Threshold Voltage analysis of raised source drain Junctionless field effect transistor

The evolution of transistor technology has led to the emergence of Junctionless Field-Effect Transistors (JLFETs) as promising alternatives to conventional MOSFETs, offering simplified fabrication and superior electrostatic control. Among them, Raised Source Drain Double gate JLFETs (RSD-JLFETs) exhibit enhanced performance characteristics, making them suitable for nanoscale applications. This paper presents a capacitance-based analytical method for accurately determining the threshold voltage of RSD-JLFETs. The model defines threshold voltage as the gate voltage at which the depletion width equals the silicon body thickness, marking the onset of conduction. Unlike traditional current-based methods, this approach utilizes the gate-to-channel capacitance transition to extract threshold voltage (Vth), incorporating critical design parameters such as gate work function, oxide thickness, channel length, dielectric constant, drain voltage, and temperature. The model is validated through extensive TCAD simulations using various high-k dielectrics and gate materials, demonstrating strong agreement with conventional techniques. The validation of the model is also done by comparison with experimental results by fabricating the device on SOI wafer. This method offers a physically insightful, computationally efficient tool for Vth estimation, aiding the design and optimization of next-generation low-power JLFET devices.