High-Speed SHDAC Design for Hybrid ADCs by Integrating 3-bit Flash and 8-bit Sigma-Delta for Improved Resolution

In the realm of rapid analog-to-digital conversion, it is not without its challenges to accomplish both high resolution and high sample rates to a satisfactory degree. The purpose of this work is to introduce a novel approach that involves combining a 3-bit Flash analog-to-digital converter (ADC) with an 8-bit Sigma-delta (ΣΔ) ADC. The overall goal of the proposed work is to develop a High-Speed and Sample Hold-Digital-Analog Converter (SHDAC), which can operate on different voltage sampled ranges from 4 to 32 scales and generate sample frequencies ranging from 3 giga-samples per second (Gsps) to 14 Gsps. The collaborative approach to two types of ADCs heavily relies on the 3-bit Flash ADC for high-speed designs with rapid conversion rates, and the 8-bit Sigma-Delta ADC for oversampling and enhanced resolution features with reduced noise compatibility. By combining these two methods, the SHDAC is able to achieve a balance between speed and resolution, which is suitable for tasks that need a high level of digital communication and signal processing. The implementation of a digital scaling mechanism that dynamically alters the SHDAC's bit resolution based on the specified scalar, which may be 4, 8, 16, or 32 bits from the beginning, is the key to the design. This versatility enables the SHDAC to meet the requirements of a wide variety of applications, ranging from lower resolution images with faster sampling to higher resolution images with slower sampling. The proposed work with SHDAC implements a novel technique with an integrated design based on a front-end model with Verilog, which provides high-precise functionality of the ADC's with better scalability and adaptability, indicating the efficient power and sampling rates achieved from 3–14 Gbps and a power of 0.01 dynamic power for the SHDAC design, as verified in the Vivado tool.