Stacked Nanowire FET for CMOS Technology Scaling

As CMOS technology nears its scaling limits, stacked nanosheet and nanowire field-effect transistors (FETs) have emerged as key candidates for extending Moore's Law. These architectures offer superior electrostatic control, reduced short-channel effects, and high drive current due to their gate-all-around (GAA) structure. Stacked configurations enhance effective channel width, providing higher performance in compact footprints. This paper analyzes the electrostatic behavior, drive current, and leakage characteristics of these devices for sub-5 nm nodes. Challenges in material integration and fabrication complexity are discussed, with simulation and experimental results supporting their potential for next-generation CMOS scaling.