Immunity to Short Channel Effects in Monolayer MoS2 Transistors via Ultrathin Contact Extension

Two-dimensional (2D) monolayer semiconductors are promising candidates for ultimately scaled electronics applications owing to their atomic-scale thickness. However, non-ideal contact geometries can fundamentally compromise their electrostatic integrity at short gate lengths, thereby masking the intrinsic scaling advantages of 2D channels. Here, we present the first experimental demonstration of ultrathin (0.3 nm) contact extensions in ultra-scaled dual-gate (DG) MoS ₂ FETs, mitigating short-channel effects (SCEs) caused by non-ideal contact geometries from contact gating structures—a key limitation in existing 2D FETs. The ultra-scaled DG devices feature channel lengths (LCH) down to 20 nm and a combined equivalent oxide thickness (EOT) of 0.75 nm, with on-currents reaching 460 µA/µm and maximum transconductance (g _m ) values reaching 206 µS/µm at a drain-to-source voltage V _DS =1 V, the highest reported for 20 nm channels. Moreover, due to the ultra-thin contact extensions, our devices exhibit near immunity to SCEs. The off-state performance specs outperform prior-reported data on 20 nm FETs, with minimal subthreshold swing (SS) degradation at 20 nm (< 25% increase compared to long-channel device), SS=97 mV/dec, drain-induced-barrier-lowering (DIBL)=30 mV/V, and a near-zero threshold voltage. This work marks a key step toward aggressively scaled logic devices based on 2D materials.