Experimental Characterization and Validation of a PLECS-Based Hardware-in-the-Loop (HIL) Model of a Dual Active Bridge (DAB) Converter

Hardware-in-the-Loop (HIL) simulation has become an indispensable tool for rapid and cost-effective development and validation of power electronic systems. This paper presents a detailed experimental characterization and validation of a PLECS-based HIL model for a Dual Active Bridge (DAB) DC-DC converter controlled using Single Phase Shift (SPS) modulation. An extensive experimental investigation is conducted to characterize the converter's performance across a wide range of operating conditions. The primary objective of this work is to validate and fine-tune the PLECS-based HIL model of a single DAB converter, laying the foundation for building more complex models, such as configurations with multiple converters connected in series or parallel. A DAB prototype has been characterized by varying the PWM phase shift angle between the input-output full-bridges over a range of equivalent input-output voltage levels. The power flow and efficiency were also analyzed at different voltage gains (M = 0.6, 1, and 1.4). In addition, the influence of key parameters like switching frequency and leakage inductance on the converter’s power flow and efficiency was experimentally evaluated. The experimental efficiency trends and power characteristics across the operating points provide valuable insight into the optimal modulation range and loss mechanisms of the DAB converter under SPS control. The HIL model is thoroughly tested against the experimental hardware prototype by comparing key metrics, including transferred power and system efficiency. The results demonstrate a high degree of accuracy between the HIL model and the physical system across all tested operating conditions. This work provides a validated, high-fidelity HIL model and a comprehensive dataset that confirms the effectiveness of the PLECS platform for the development and optimization of DAB converters, thereby reducing design time and mitigating risks in subsequent prototyping stages.