Universal Logic-In-Memory Gates using Reconfigurable Silicon Transistors

This study aims to implement universal logic gates using polarity control within a single silicon transistor structure. For this purpose, a reconfigurable transistor based on a p-i-n structure featuring two polarity gates (PGs) and one control gate was proposed, and its electrical characteristics and logic-in-memory (LIM) circuit operations were analyzed via two-dimensional technology computer-aided design simulations. The proposed device could be perfectly reconfigured into p-channel or n-channel modes because virtual doping effects could be induced according to the polarity of the PG voltage. Moreover, based on the positive feedback and latch-up phenomena, a steep subthreshold swing of approximately 1 mV/dec and a high ON/OFF current ratio of the order of 10^10 were achieved. Building on these characteristics, we successfully verified NAND LIM operation in the p-channel mode and NOR LIM operation in the n-channel mode by connecting two of the proposed devices in parallel. The reconfigurable silicon transistor proposed in this study could perform both NAND and NOR LIM operations while sharing the same device structure and can be expected to play a key role in implementing high-density, low-power LIM systems in the future.