A Survey of Machine and Deep Learning Techniques in Analog Integrated Circuit Layout Synthesis

Automatic techniques for analog integrated circuit layout design have been proposed in the literature for over four decades. However, as analog design moved into deep nanometer integration nodes, the increasing number of design rules, layout-dependent effects influence, congestion, and parasitic structures impact is constantly challenging existing automatic layout generation techniques and keeping pressure on their further improvement. At the time of writing, no automatic tool or flow has established in the industrial environment, resulting in a time-consuming and difficult-to-reuse design process. However, very recently, machine and deep learning techniques started to offer solutions for problems not dealt with in the previous generation of automatic layout tools and are reshaping analog design automation. Therefore, this paper conducts a review of most recent analog integrated circuit automatic layout techniques powered by machine and deep learning methods, covering placement, routing, and trends on post-layout performance estimation, providing an actual, complete and comprehensive guide for circuit designers and design automation developers.